General Description

The MW_ATSC modulator core performs the digital baseband function for the transmission side of new generation Digital Video Broadcasting in the United States. It implements the framing functions as defined by A/53: ATSC Digital Television Standard, Parts 1-6, 2007. The MW_ATSC core is designed to achieve high performance for a single chip FPGA based design, including control and status management. 8VSB is used as the terrestrial transmission format. The modulator using eight discrete amplitude modulation levels, that are assigned eight different symbol values, to convey the MPEG compressed transport stream. It supports a payload data rate of 19.39 Mb/s in a 6 MHz channel. The input to the transmission subsystem from the transport subsystem is a data stream comprised of 188 byte MPEG-2. Internal 20-bit architecture for high level MER and BER performances is provided. A larger capability could be obtained using additional FPGA resources. FPGA netlist only or complete design environment package are deliverable. The core was developed in Vivado tool, written in HDL code.

Features

• Fully-hardware implementation of the standard IP stack avoids the need of extra software development and resulting bottlenecks
• It supports any appliance requiring conversion of data to IP and vice versa
• Transport Streams video flows can be easily adapted to IP transportation
• MindWay provides a complete ecosystem of available Cores that allow you to build lots of IP-based video applications
• Multiple instances of MW_HPS in a single FPGA permit to easily implement networking functionalities (bridging and routing, HW servers, protocol adapters, etc.), dramatically reducing design complexity and costs
• Inexpensive implementation with reduced FPGA resources (the limited size of the core leaves enough space for other complex functions, such as modulator, data compressors, crypto engines, etc.)

Typical Application